I need to implement a 32 bit adder subtractor ALU for a class assignment. I have a 1-bit adder subtractor that works fine and the operation is made with the help of a select statement (code for all is given below). Anyway, the problem I am facing is that I am unable to figure out how to use the carry/borrow out of one module to the subsequent module. Module add_sub(select, i0, i1, cin, out, cout ); input i0, i1, select, cin; output out, cout; wire y0, y1, y2, y3, y4, y5, y6; wire z0, z1, z2, z3, z4; //diff = i0 xor i1 xor cin //borrow = cin.
~(i1 xor i2) or ~x.y xor (y0, i1, cin); xor (y1, i0, y0); //y1=diff or sum as only carry and borrow vary between adder and subtractor circuits xor (y2, i1, i0); and (y3, cin, ~y2); and (y4, ~i0, i1); or (y6, y5, y4); //y6 = borrow and (z0, i0, i1); xor (z1, i0, i1); and (z2, cin, z1); or (z3, z0, z2); //z3= carry out for sum //conditional operator for assigning sum or difference. If select = 0, we add, else subtract assign out = y1; assign cout = select? Y6: z3; endmodule This module is instantiated in a loop in the alu module that is given below. Module alu(sel, num1, num2, alu_cin, alu_out, alu_c ); parameter N = 32; input sel; //select line for add or sub input [N-1:0] num1; //two inputs input [N-1:0] num2; input alu_cin; output [N-1:0] alu_out; //32 bit output output alu_c; // becomes final carry or borrow accordingly genvar i; generate for (i=0; i.
It is syntactically correct but you are using a bit-select on a single bit value, which is a semantic error. Add_sub as_i ( sel,num1[i],num2[i],alu_loop[i-1]. Boinx Fotomagico Crack on this page. as_i.cout[i-1],alu_out[i],alu_c); ^^^^ Declared as scalar output in add_sub output out, cout; While Verilog allows referencing a port using the dot notation(hierarchical referencing), it's not a good practice outside of testbenches. You should declare a wire for that connectivity instead.